the typical trade-off that exists between risc and cisc can be expressed in the total time required to execute a certain task: time (task) = i x c x p x t0 i = no. of instructions / task c = no. of cycles / instruction p = no. of clock periods / cycle (usually p=1) t0 = clock period (ns) while cisc instruction will typically have less … Contents Figures .. . vii T ables .. . ix About this document .. . xi Who should use this manual .. . xi Pr ogramming interface information .. . xi Influence of Technology and Software on Instruction Sets: Up to the dawn of IBM 360 (A) L3 Complex Instruction Set Evolution in the Sixties: Stack and GPR Architectures (A) L4 Microprogramming (A) L5 Simple Instruction Pipelining (A) L6 Pipeline Hazards (A) Module 2: L7 Multilevel Memories - Technology (J) L8 The IBM RS/6000 shares with older RISC designs the streamlined approach to pipelined execution. But the instruction set of the IBM processor is large and many special instructions have been provided in order to speed up execution. The POWER chip set is indeed an impressive computing engine. The RS/6000 is a 32 bit processor. REDUCED INSTRUCTION SET COMPUTERS Prof. Vojin G. Oklobdzija Integration Berkeley, CA 94708 (IBM) Corporation announcing IBM System/360 computer family on April 7, 1964 [1,17]. On that day IBM Corporation IBM RS/6000 (also known as PowerPC architecture). V.G. Oklobdzija Reduced Instruction Set Comput ers 4 1.2. RISC Performance RXE format provide the same register, base, index, and displacement fields as the RX format, however the opcode is 16 bits - split between the first and last bytes of the instruction. Bits 32-39 of the instruction are reserved. With the advent of z/Architecture, the RS instruction format was similarly extended to form the RSE format. 1) The program is in core at absolute location 48 2) The 20 adjacent full words are starting at absolute location 900 3) The number 50 to be added is at absolute location 896 3) The number 20 is at Abstract The architecture of the newly announced IBM System/360 features four innovations: 1. An approach to storage which permits and exploits very large capacities, hierarchies of speeds, This text introduces the student to the architecture of System/360. Such System/360 features as channels, automatic interrupts, and general purpose registers are presented. Storage addressing, instruction formats, data formats, and the various types of arithmetic opera­ tions are also discussed. Two Address IBM 360 Instruction Format: R1 <-- R1 op R2 Major dependence 6mechanisms: - (5 RS x 2) + 4 FLR + 3 SDB : CDB has 17 destinations • Electrically very challenging - 3 physical sources must arbitrate for access to CDB - Tag + data must be driven to 17 destinations - Modified IBM 360/91 Floating -point Unit - Reservation Stations - Common Data Bus Two Address IBM 360 Instruction Format: R1 <-- R1 op R2. - (5 RS x 2) + 4 FLR + 3 SDB : CDB has 17 destinations • Circuit design very challenging Instruction Format Example • Size of the instructions are as follows: - RR is 2 bytes - RX, RS and SI are 4 bytes each - SS is 6 bytes • Example 1: AR 3, 4 can occupy 2 bytes as follows: • This instruction causes the contents of general register 4 (32 bits) to be added to the contents of general register 3 (32 bits) and the sum will Instruction Format Example • Size of the instructions are as follows: - RR is 2 bytes - RX, RS and SI are 4 bytes each - SS is 6 bytes •